Offset-calibration with Time-Domain Comparators Using Inversion-mode Varactors

This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective lines can be adjusted with a set of digitally-controlled inversion-mode varactors. These varactors provide tuning capabilities to the comparator; feature which can be exploited for offset calibration. This is demonstrated with the implementation of a differential 10-bit SAR-ADC. The design, fabricated in a 0.18μm CMOS process, includes an automatic mechanism for adjusting the capacitance of the varactors in order to calibrate the offset of the whole converter. Correct functionality was measured in all samples.Ministerio de Economía y Competitividad TEC2016-80923-POffice of Naval Research (USA) N0001414135

A Lime-Flavored REST API for Alignment Services

A practical alignment service should be flexible enough to handle the varied alignment scenarios that arise in the real world, while minimizing the need for manual configuration. MAPLE, an orchestration framework for ontology alignment, supports this goal by coordinating a few loosely coupled actors, which communicate and cooperate to solve a matching task using explicit metadata about the input ontologies, other available resources and the task itself. The alignment task is thus summarized by a report listing its characteristics and suggesting alignment strategies. The schema of the report is based on several metadata vocabularies, among which the Lime module of the OntoLex-Lemon model is particularly important, summarizing the lexical content of the input ontologies and describing external language resources that may be exploited for performing the alignment. In this paper, we propose a REST API that enables the participation of downstream alignment services in the process orchestrated by MAPLE, helping them self-adapt in order to handle heterogeneous alignment tasks and scenarios. The realization of this alignment orchestration effort has been performed through two main phases: we first described its API as an OpenAPI specification (a la API-first), which we then exploited to generate server stubs and compliant client libraries. Finally, we switched our focus to the integration of existing alignment systems, with one fully integrated system and an additional one being worked on, in the effort to propose the API as a valuable addendum to any system being developed

A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications

This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2nW at 4kS/s and achieves 9.5 ENOB.Ministerio de Economía y Competitividad TEC2012-33634Office of Naval Research (USA) N0001414135

A Sub-µW Reconfigurable Front-End for Invasive Neural Recording

This paper presents a sub-μW ac-coupled reconfigurable front-end for the purpose of neural recording. The proposed topology embeds in it filtering capabilities allowing it to select among different frequency bands inside the neural signal spectrum. Power consumption is optimized by designing for bandwidth-specific noise targets that take into account the spectral characteristics of the input signal as well as the noise bandwidths of the noise generators in the circuit itself. An experimentally verified prototype designed in a 180 nm CMOS process draws a maximum of 815 nW from a 1 V source. The measured input-referred spot-noise at 500 Hz is 75 nV/√Hz while the integrated noise in the 200 Hz - 5 kHz band is 4.1 μVrms.Ministerio de Economía y Competitividad TEC2016-80923- PJunta de Andalucía TIC 233

A High TCMRR, Inherently Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation

This paper describes a multichannel bidirectional front-end for implantable closed-loop neuromodulation. Stimulation artefacts are reduced by way of a 4-channel H-bridge current source sharing stimulator front-end that minimizes residual charge drops in the electrodes via topology-inherent charge balancing. A 4-channel chopper front-end is capable of multichannel recording in the presence of artefacts as a result of its high total common-mode rejection ratio (TCMRR) that accounts for CMRR degradation due to electrode mismatch. Experimental verification of a prototype fabricated in a standard 180 nm process shows a stimulator front-end with 0.059% charge balance and 0.275 nA DC current error. The recording front-end consumes 3.24 µW, tolerates common-mode interference up to 1 Vpp and shows a TCMRR > 66 dB for 500 mVpp inputs.Ministerio de Economía y Competitividad TEC2016-80923-POffice of Naval Research (USA) N00014111031

Improving the accuracy of RF alternate test using multi-VDD conditions: application to envelope-based test of LNAs

Trabajo presentado al "20 Asina Test Symposium" celebrado en Nueva Delhi (India) del 20 al 23 de Noviembre del 2011.-- Reprinted from (relevant publication info). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the products or services of CSIC Spanish National Research Council, Digital.CSIC. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.This work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning mod- els, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Post- layout simulation results are provided to verify the functionality of the approach. Copyright © 2011 IEEE.This work has been partially funded by a CSIC JAE-Doc contract (cofinanced by FSE), a Spanish MAE-AECID grant and projects: SR2 - Short Range Radio (Catrene European project 2A105SR2 and Avanza I+D Spanish project TSI-020400-2010-55, cofinanced with FEDER program), Auto-calibración y auto-test en circuitos analógicos, mixtos y de radio frecuencia (Andalusian Government project P09-TIC-5386, cofinanced with FEDER program), and Catrene project TOETS (CT 302).Peer reviewe

Mixed-signal quadratic operators for the feature extraction of neural signals

This paper presents design principles for reusing charge-redistribution SAR ADCs as digital multipliers. This is illustrated with an 8-b fully-differential rail-to-rail SAR ADC/multiplier, designed in a 180 nm HV CMOS technology. This reconfigurability property can be exploited for the extraction of product-related features in neural signals, such as energy content, or for the discrimination of spikes using the Teager operator.Ministerio de Economía y Competitividad TEC2012-33634Office of Naval Research (USA) N0001414135

A 32 Input Multiplexed Channel Analog Front-End with Spatial Delta Encoding Technique and Differential Artifacts Compression

This paper describes a low-noise, low-power and high dynamic range analog front-end intended for sensing neural signals. In order to reduce interface area, a 32-channel multiplexer is implemented on circuit input. Furthermore, a spatial delta encoding is proposed to compress the signal range. A differential artifact compression algorithm is implemented to avoid saturation in the signal path, thus enabling reconstruct or suppressing artifacts in digital domain. The proposed design has been implemented using 0.18 μm TSMC technology. Experimental results shows a power consumption per channel of 1.0 μW, an input referred noise of 1.1 μVrms regarding the bandwidth of interest and a dynamic range of 91 dB.Ministerio de Economía y Competitividad TEC2016-80923-POffice of Naval Research ONR N00014- 19-1-215

Does the Baroudi-Ferreira technique reduce seroma after abdominoplasty?

Introduction: Abdominoplasty has evolved over the years with improvement of techniques that initially had high complication rates. However, even with the evolution of operative techniques, seroma remains the most frequent early complication of this procedure. This study aims to compare the development of seroma after abdominoplasty with and without the use of quilting sutures. Methods: Twenty patients undergoing abdominoplasty were evaluated and divided into two groups: Group A (abdominoplasty using quilting sutures - Baroudi-Ferreira technique) and Group B (abdominoplasty without the use of quilting sutures). Results: Two patients in Group A (20%) had seroma, which was significantly lower (p = 0.05) than that in Group B, in which seven patients were diagnosed with seroma (70%). The mean volume observed in Group A was 26.5 mL, whereas in Group B, it was 146.5 mL. The highest volume aspirated in Group A was 130 mL, on the 15th postoperative day (POD), whereas in Group B it was 230 mL, on the 21st POD. Conclusion: In this study, the development of seroma in abdominoplasty was significantly lower in the group in which the Baroudi-Ferreira technique was used